The insulated gate bipolar transistor (hereinafter IGBT) is an integrated combination of a bipolar transistor and a metal oxide semiconductor field effect transistor and has become commercially successful due to its superior on-state characteristics and excellent safe-operating area. IGBTs in integrated circuits are commonly configured as lateral insulated gate bipolar transistors (hereinafter LIGBTs) and fabricated using a planar process sequence to minimize cost and complexity of the integrated circuit manufacturing operation.
FIG. 1A is a cross cross cross sectional view showing a conventional LIGBT 100 of prior art. The LIGBT 100 of FIG. 1A comprises: a P-substrate 101; an N epitaxial layer 103 on top surface of the P-substrate 101; a P buried layer 102 with higher doping concentration than the P-substrate 101 and located at a part of the top surface of the P-substrate 101 and beneath an n+ source (cathode) region 107 near top surface of the N epitaxial layer 103; a p++ source contact doped region 105 provided in the N epitaxial layer 103 and adjacent to a p body region 104 and the n+ source region 107. A channel region of the illustrated LIGBT 100 is formed near top surface of the p body region 104 between the n+ source region 107 and the N epitaxial layer 103; a p+ anode region 108 located near the top surface of the N epitaxial layer 103 and spaced apart from the p region 104; a source metal 111 and a drain metal 113 contacted with the n+ source (cathode) region 107 and the p++ source contact doped region 105, and the p+ anode region 108 by planar contact, respectively. The LIGBT 100 of FIG. 1A offers several important advantages over lateral diffusion metal oxide semiconductor, including high current handling capabilities, low on-resistance and high breakdown voltage. However, it has suffered from a significant drawback of switching speed because there is no n+ drain region provided for removal of electrons (minority carriers) during turn-off process. During turn-on process, the p+ anode region 108 injects holes (majority carriers) into drift region and the n+ source (anode) region 107 injects electrons into the drift region through the channel to form a low-resistance plasma modulation region. During turn-off process, the holes in the plasma modulation region are removed by flowing through the p+ anode region 108 but the electrons are removed by recombination of the electrons and the holes. Therefore, the turn-off process is determined by the recombination of electrons, and since no contact is provided for the removal of the electrons, the turn-off time is relatively long in the range of 3-10 microseconds, while turn-on time is much less than 1 microsecond.
A typical prior art fast switching LIGHT 200 is shown in FIG. 1B. Similar fast switching LIGHTs are shown in U.S. Pat. No. 4,989,058. Besides those in common with the LIGHT 100 of FIG. 1A, the LIGHT 200 of FIG. 1B comprises an additional n+ drain region 209 adjacent to the p+ anode region 208 to remove the electrons (minority carriers) during the turn-off process as discussed above. Therefore, the turn-off time of the LIGHT 200 of FIG. 113 is shorter than that of the LIGHT of FIG. 1A. However, the LIGHT 200 has its own constrain which is that on-resistance is significantly increased because triggered voltage Vds for holes (majority carriers) injection is larger than the typical value of 0.7 V for the LIGHT 100 as shown in FIG. 2 due to an additional resistance Rp (as illustrated in FIG. 1B) existing underneath the p+ anode region 208 besides Rd (as illustrated in FIG. 1A and FIG. 1B). The Triggered voltage Vds is: I*(Rd+Rp)=IRd+IRp≈IRd+0.7 V>0.7 V, where I is the current flowing through the drift region to the n+ drain region 209. From FIG. 2 it can be seen that, the triggered voltage Vds of the LIGHT 100 is about 0.7V and the triggered voltage Vds of the LIGHT 200 is about 1.2 V as shown in FIG. 2.
Accordingly, it would be desirable to provide a new and improved LIGHT that has both low on-resistance and high switching speed.